The present invention relates to a semiconductor memory device, and more particularly to a circuit for generating an internal source voltage in a semiconductor memory device.
As semiconductor memory devices have become more highly integrated, the memory cells in the memory devices have become increasingly miniaturized. Hence, if an external voltage supplied to the memory device is not properly adjusted, a strong electric field may be formed which will cause a stress to be applied to the memory device, thereby damaging the memory elements. The semiconductor memory devices having 16 Megabits should employ a circuit for generating an internal voltage to drop the level of the external voltage to the level of the operating voltage of the memory device. For example, semiconductor memory devices over 16 Megabits should use an internal voltage of 4V which is usually obtained by dropping the external voltage of 5V.
FIG. 1 shows a conventional circuit for generating an internal source voltage according to prior art. This circuit includes a reference voltage generating circuit 100 for generating a reference voltage Vrefs. Comparator 200 compares the internal source voltage int.Vcc with the reference voltage Vref. A driver 90 couples the external voltage ext.Vcc to the internal source voltage int.Vcc under the control of the comparator 200 and a burn-in reference voltage generating circuit 300. The internal source voltage int.Vcc is applied to the memory elements of the memory device, as well as, to an NMOS transistor N2 of the comparator 200. If the internal source voltage int.Vss drops below the reference voltage Vref, the level of the output signal G1 of the comparator 200 drops so as to fully turn on the driver 90 to compensate for the dropping internal source voltage int.Vcc. Alternatively, if the internal source voltage int.Vcc is increased above the reference voltage Vref, the output signal G1 of the comparator 200 is increased so as to turn off the driver 90 to permit the internal source voltage int.Vcc to drop to the reference voltage Vref.
If the voltage level of the external source voltage ext.Vcc is higher than the voltage level of the burn-in reference voltage, the burn-in reference voltage generating circuit 300 generates an output signal G3 having a logic "high" state so as to turn off transmission gates N4, P3 through inverters I1 and I2 and turn on a pull down transistor N5, so that the external source voltage ext.Vcc is applied to the memory device through the driver 90. In this case, since the transmission gate N4, P3 is turned off, the output signal G1 of the comparator 200 does not affect the signal G2 which is applied to a gate of the driver 90.
In such a conventional circuit for generating the internal source voltage, if the voltage level of the external source voltage ext.Vcc is lower than the voltage level of the reference voltage Vref, the transmission gate N4, P3 is turned on so as to cause the output signal G1 of the comparator to affect the driver 90. Consequently, when the internal source voltage int.Vcc is changed by a peak current generated in the memory drive, the voltage G2 changes so as to instantly drop the internal source voltage int.Vcc below the external source voltage. Thus, the operating speed of the memory elements is slowed down to cause an improper functioning of the memory.